从一年前开始Haswell-EP的发展热火朝天了好一阵子，第一轮工程样品目前运行良好。像Ivy Bridge-EP、Haswell-EP、正式版Xeon E5v3这些增加了的包括低核高频、高核低频芯片成员，适用于各类工作站、服务器、超级计算机和大数据处理。
Ivy Bridge-EP拥有6核和10核两种版本及从EX系列借用的12核，Haswell-EP至少包括8核及14核版本—尚未确定是否“借用16+核 Hawell-EX”的顶级核心数，这意味着又是一个单独的12核“本土”Haswell EP主产品线。随着未来几个月系统启动OEM（原始设备厂商）及关键用户采样，我们很快就将知道答案。这轮采样将耗费英特尔更多的验证和努力，像其他如DDR4内存、9.6GT/s的QPI、原生USB3、SAS12G及PCle SSD等新产品将同时为配套系统推出。
假设时钟速率与目前的E5v2一致，最顶级为Xeon E5v3，其正式推出可能在（或早于）下一次旧金山英特尔秋季开发者论坛（Intel Fall IDF）。双插槽FP每槽将达到700GFLOP或1.4TFLOP双槽板—如果没有高超的CUDA或OpenCL编码能力，任何高端GPU都很难达到这一程度。
2015年英特尔将推出Xeon Pi。Xeon CPU在2015年年中将发展为“BroadwellEP”Xeon E5v4，第一款采用14nm制程的高端Xeon芯片。多达18核、每插槽可达45MB L3并配备更快的存储，不知将会如何影响芯片行业的竞争。（元器件交易网毛毛 摘译）
What does the future hold for themainstream Xeon processor line? Will it face the roadmap uncertainties ofoff-the-shelf desktop CPUs for the next year or two?
After a bit of slowdown that seems to haveresulted from both lack of competition, and the teething troubles of the 22 and14nm process, the next few rounds are proceeding at full speed.
Why such a change? After all, it"s not asif AMD seems to be getting back into the high-end field, to everyone"sdisappointment (and no, they cannot blame anyone else but themselves). WhileARM is nowhere as efficient as the old Alpha or MIPS were when it comes tohigh-compute jobs, the money power that ARM now sits on, supported by its richand powerful vendors, does drool at the royal margins that Intel earns of itsfour-digit priced Xeons, compared to pitiful few bucks to few dozen dollarsthat ARM processors go for.
The heavyweights like Samsung, Huawei,Apple, Qualcomm and Nvidia, plus a number of ARM-specific niche CPU makers –AMD included – are trying to aim for this market.
Intel had a very successful Ivy BridgeXeon-EP (officially known as Xeon E5-2600 v2) rollout this past quarter. Boththe 8-core E5-2687Wv2 (3.4 GHz before Turbo, mind you), the main high end10-core 3 GHz E5-2690v2, and the 12-core 2.7 GHz E5-2697v2, supposedly acut-down 15-core Xeon E7v2, are all sold out – and these are just thehighest-ASP SKUs. I"ve worked with few of these speed bins on variousworkstation and HPC loads, with both DDR3L-1600 and DDR3-1866 memory, and itscache and memory subsystems are so effective that the actual memory choicedoesn"t seem to matter much in most benchmarks.
The next few months will keep them busyintroducing the four-socket Xeon EP v2 versions, as well as multi-socket XeonEX v2, the 15-core monsters with 37.5 MB L3 and triple QPI channels per socket,covered here before.
So, what comes after them?
As explained a year ago, Haswell-EPdevelopment was in full swing for quite a while, and the first round ofengineering samples seems to run very well. Just like Ivy Bridge-EP, theHaswell EP, officially Xeon E5v3, will have multiple die flavours to addressboth low-core count but high MHz, and high core count at less MHz, for variousworkstation, server and supercomputer and big data workloads.
While the Ivy Bridge-EP had 6-core and10-core dies, with the 12-core flavor borrowed from the EX line, the Haswell-EPwill have 8-core and 14-core dies at least – where it"s not confirmed yet ifthe top core-count die is also “borrowed from the 16+ core Haswell-EX”, meaningthere is again a separate say 12-core main line “native” Haswell EP. We"ll knowsoon, as the systems start sampling to the OEMs and critical users over thenext few months. This round of sampling will take Intel a bit more validationcare and effort, since many other new things like DDR4 memory, sped-up 9.6 GT/sQPI, native USB3, SAS12G and PCIe SSDs will be rolled out at the same time intothese systems.
Assuming the clock rates stay similar tothe current E5v2, the top end of the Xeon E5v3, when they officially surfacelikely at (or just before) the next Intel Fall IDF in San Francisco, will beable to achieve close to 700 GFLOPs in double precision FP per socket, or 1.4TFLOPs for a typical dual socket board – something that any top end GPU wouldhave hard time matching, and this is without esoteric CUDA or OpenCL coding.
Even the 8-core enthusiast desktopHaswell-E, Core i7 59xx, will be able to give close to half a teraflop indouble precision without much overclocking – the FMA fused multiply add extrasdo help here, something that 64-bit MIPS architecture had for over 15 yearsnow, by the way.
Then we come to 2015, the same year whenthe next Xeon Phi would come out. The Xeon CPU to match it in the middle ofthat year will be “Broadwell EP” Xeon E5 v4, the first high end Xeon to be madein 14nm process. How about up to 18 cores and 45 MB L3 per socket, coupled witheven faster memory? How will its innovations impact the competition?